As integrated circuit structures have become increasingly complex, it has become necessary to provide multiple levels of interconnection. While the use of a metallic interconnection layer is preferred from the point of view of high conductivity, metallic layers are incapable of withstanding the high temperatures that characterize some of the process steps. Accordingly, it has become standard practice to use refractory materials such as metal silicides for interconnection where subsequent high temperature steps are to be carried out.
One of the major characteristics of the progress in intergrated circuit technology has been a dramatic decrease in the size of the circuit elements on the wafer. However, making the elements smaller is not a matter of merely scaling the dimensions. As the transverse dimensions (the dimensions in the plane of the wafer) are decreased, the ultimate circuit performance becomes increasingly sensitive to minor mask misalignment during processing. At the same time, the increases in circuit complexity and the number of interconnection layers have required a greater number of masking steps, thereby compounding the problem.
For example, in the prior art, a quasi-buried contact ("QBC") between a polycrystalline silicon ("polysilicon") layer and an underlying doped region in the silicon substrate has required that the two materials interface over a certain minimum area if low resistance contact is to be achieved. This stringent requirement of positive overlap renders the circuit structure highly sensitive to possible mask misalignment.
A typical application of a quasi-buried contact is to connect a polysilicon load resistor to the drain of an FET in a memory cell. In the prior art, the load resistor is typically made by providing a polysilicon layer having spaced interconnection regions and an intermediate resistor region, lightly doping the resistor region of the layer, and heavily doping the spaced interconnection regions of the layer. However, when the wafer is subjected to subsequent high temperature process steps, dopant from the interconnection regions diffuses laterally into the lightly doped polysilicon, thereby reducing the effective resistor length in a manner that may be difficult to control. This lateral diffusion further places a lower limit on the resistor dimensions. Moreover, depending on the particular process chosen, the resistor parameters (depending as they do on the transverse extent of the lightly doped portion of polysilicon layer) may be sensitive to possible mask misalignment.
Accordingly, there are ever-present in the art a need either to reduce the number of masking steps, or to provide additional functions or benefits without increasing the number of masking steps, and a need to reduce critical dependency on mask alignment.